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| S3C49F9X SOLID DISK CONTROLLER INRODUCTION S3C49F9X User's Manual (Compact Flash Controller) Samsung Electronics Co.,LTD Semiconductor LSI System Division 1 S3C49F9X SOLID DISK CONTROLLER INRODUCTION 1 PRODUCT OVERVIEW Samsung's S3C49F9X is NAND flash memory controller which can control flash memories as solid state disk. It provides PC Card ATA/IDE interface, host and flash transfer rates up to 20.0MB/S. S3C49F9X can control flash memory maximum 10 pieces if use the 32M,64M,128M,512Mbit and can control flash memory maximum 8 pieces if use the 1Gbit. The device is designed using 0.35-um CMOS process, housed in a 100-TQFP package. It supports operation in both 5.0V and 3.3V. An outstanding feature of the S3C49F9X flash disk controller is its CPU core: the ARM7TDMI 16/32-bit RISC processor, designed by Advanced RISC Machine (ARM), Ltd. The ARM core is a low-power, general purpose, microprocessor macro-cell that was developed for use in application-specific and customer-specific intergrated circuit. It is simple, elegant, and fully static design is particularly suitable for cost and power sensitive application 1.1 Features - PC Card-ATA/True IDE/CompactFlash compatible host interface - Automatic sensing of PC Card ATA and 68-pin IDE - Included 256-byte CIS RAM - Five PC Card ATA addressing modes - Host data transfer rate : 20MB/S - Flash data transfer rate : 10MB/S - Host Interface : 8/16-bit Access - Flash Interface : 8-bit Access - Support 3 power save mode : stop/idle/active - Support up to 10 flash memories - Support 32/64/128/256/512Mbit,1Gbit NAND flash memory made by Samsung NAND Flash Density 32Mb, 64Mb, 128Mb, 256Mb, 512Mb 1Gb - Auto power down function - ECC function - Available 100-pin TQFP - Operating Voltage : 3.3V to 5.0V Min. / Max. Capacity (number of flash) 4MB / 512MB (Up to 10ea) 128MB/1GB (Up to 8ea) 2 S3C49F9X SOLID DISK CONTROLLER INRODUCTION Microprocessor Architecture - 16/32-bit RISC architecture - Efficient and powerful ARM7TDMI CPU core - Cost-effective JTAG based debug solution Interrupts - 8 interrupt sources - Normal or fast interrupt modes (IRQ, FIQ) System Manager 512-Kbyte virtually addressable memory PC-Card/ATA Interface - Include 256-Bytes SRAM for CIS - Support memory and I/O addressing mode - Support True IDE mode - 1-bit ECC space - Support 8/16-bit external bus for SRAM/ROM - Programmable external memory access time - Included 32-Kbytes internal ROM - Included 8-Kbytes internal SRAM DMA Controller - Two-channel, general-purpose DMA controller - Memory to memory, PCMCIA to/from memory data transfers without CPU Intervention - Support for 8/16-bit data transfers - Increment or decrement of source or destination address Operating Voltage Range - 3.3 to 5.0 volts Programmable Timer - 1-channel 16-bit programmable timer Operating Frequency - Up to 20MHz Package Type - 100-TQFP 3 S3C49F9X SOLID DISK CONTROLLER INRODUCTION 1.2 Block Diagram LOCAL BUS ARM7TDMI MASK ROM CPU CORE (32KB) BUS ROUTER DMA0 ADDRESS Decoder PCMCIA/ DMA1 ATA CIS (256Byte) INTERRUPT Controller TIMER S-BUS SYSTEM MANAGER BUS INTERFACE BUS ARBITRATION SYSTEM BUS controller MEMORY Controller (SRAM) SRAM (8KB) 4 S3C49F9X SOLID DISK CONTROLLER PIN INFORMATION 2 VDD7 FCE7 FCE8 FCE9 TDO nTRST TEST1 TEST2 GND6 TDI TMS TCK GND7 XDB10 XDB9 XDB8 XDB2 XDB1 XDB0 PVDD2 XIOIS16 XSTSCHG XDASP XREG XINPACK PIN INFORMATION 2.1 Controller Package Drawing VDD5 VDETO FDB1 FDB2 FDB3 VDD6 FDB4 FDB5 FDB6 FDB7 GND4 Xin Xout GND5 FCE0 FCE1 FCE2 FCE3 FCE4 FCE5 FCE6 FWP FPWR CTEST XTEST 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 S3C49F9X 100-TQFP (Top View) 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 FDB0 GND3 FALE0 FCLE0 FRE0 FWE0 FRDY0 VDD4 FALE1 FCLE1 FRE1 GND2 FVPP XDB3 XDB4 XDB5 XDB6 XDB7 PVDD1 XDB11 XDB12 XDB13 XDB14 XDB15 VDD3 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 GND1 XCE2 XCE1 XADR10 XOE XIORD XIOWR XADR9 XADR8 VDD2 XWE XRDY XADR7 XADR6 XADR5 nRESET XADR4 XADR3 XADR2 XADR1 XADR0 VDD1 XDS XRESET XWAIT Figure 2-1 S3C49F9X Pin Assignment 5 S3C49F9X SOLID DISK CONTROLLER PIN INFORMATION 2.2 Controller Pin Assignments and Pin type Table 2-1 Controller Pin Assignments Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 XWAIT XRESET XDS VDD1 XADR0 XADR1 XADR2 XADR3 XADR4 nRESET XADR5 XADR6 XADR7 XRDY XWE VDD2 XADR8 XADR9 XIOWR XIORD XOE XADR10 XCE1 XCE2 GND1 VDD3 XDB15 XDB14 XDB13 XDB12 XDB11 PVDD1 XDB7 XDB6 XDB5 XDB4 XDB3 O I I I I I I I I I I I O I I I I I I I I I I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O O1 I1 I5 I1 I1 I1 I1 I1 I3 I1 I1 I1 O1 I2 I1 I1 I2 I2 I2 I1 I2 I2 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 Wait of PCMCIA Write protect of flash chips for flash bus 0,1 Device select for IDE System power Address bus of PCMCIA Address bus of PCMCIA Address bus of PCMCIA Address bus of PCMCIA Address bus of PCMCIA System power reset Address bus of PCMCIA Address bus of PCMCIA Address bus of PCMCIA Ready(IREQ) of PCMCIA Write enable of PCMCIA System power Address bus of PCMCIA Address bus of PCMCIA IOWR of PCMCIA IORD of PCMCIA Output enable of PCMCIA Address bus of PCMCIA Card enable1 of PCMCIA Card enable2 of PCMCIA Ground System power Data bus of PCMCIA Data bus of PCMCIA Data bus of PCMCIA Data bus of PCMCIA Data bus of PCMCIA PCMCIA power Data bus of PCMCIA Data bus of PCMCIA Data bus of PCMCIA Data bus of PCMCIA Data bus of PCMCIA Signal Name Pin Type I/O Type Function 6 S3C49F9X SOLID DISK CONTROLLER PIN INFORMATION 38 FVPP - - High voltage power for OTP Table 2-1 Controller Pin Assignments (Cont.) Pin Number 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 GND2 FRE1 FCLE1 FALE1 VDD4 FRDY0 FWE0 FRE0 FCLE0 FALE0 GND3 FDB0 VDD5 VDETO FDB1 FDB2 FDB3 VDD6 FDB4 FDB5 FDB6 FDB7 GND4 XI XO GND5 FCE0 FCE1 FCE2 FCE3 FCE4 FCE5 FCE6 FWP FPWR CTEST I/O I/O I/O I/O I/O I/O I/O I/O I/O O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O O I B9 B5 B5 B5 B9 B9 B5 B5 B7 O2 B7 B7 B7 B7 B7 B7 B7 OSC OSC B3 B3 B3 B3 B3 B3 B3 B5 O2 I4 Ground Read enable flash chips of flash bus1 Command latch enable of flash chips of flash bus1 Address latch enable of flash chips of flash bus1 System power Ready signal of flash chips of flash bus0 Write enable of flash chips of flash bus0 Read enable flash chips of flash bus0 Command latch enable of flash chips of flash bus1 Address latch enable of flash chips of flash bus1 Ground I/O of flash chips of flash bus0,1 System power Voltage detect output I/O of flash chips of flash bus0,1 I/O of flash chips of flash bus0,1 I/O of flash chips of flash bus0,1 System power I/O of flash chips of flash bus0,1 I/O of flash chips of flash bus0,1 I/O of flash chips of flash bus0,1 I/O of flash chips of flash bus0,1 Ground Input clock Output clock Ground Chip enable 0 of flash chips of flash bus0,1 Chip enable 1 of flash chips of flash bus0,1 Chip enable 2 of flash chips of flash bus0,1 Chip enable 3 of flash chips of flash bus0,1 Chip enable 4 of flash chips of flash bus0,1 Chip enable 5 of flash chips of flash bus0,1 Chip enable 6 of flash chips of flash bus0,1 Write protect of flash chips of flash bus 0, 1 Power control signal for flash memory Core test mode select signal Signal Name Pin Type I/O Type Function 7 S3C49F9X SOLID DISK CONTROLLER PIN INFORMATION 75 XTEST I I4 Test input for test mode Table 2-1 Controller Pin Assignments (Cont.) Pin Number 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 VDD7 FCE7 FCE8 FCE9 TDO nTRST TEST1 TEST2 GND6 TDI TMS TCK GND7 XDB10 XDB9 XDB8 XDB2 XDB1 XDB0 PVDD2 XIOIS16 XSTSCHG XDASP XREG XINPACK I/O I/O I/O O I I I I I I I/O I/O I/O I/O I/O I/O I/O I/O I/O I O B3 B3 B3 O2 I4 I4 I4 I4 I4 I4 B1 B1 B1 B1 B1 B1 B1 B1 B4 I2 O1 System power Chip enable 7 of flash chips of flash bus0,1 Chip enable 8 of flash chips of flash bus0,1 Chip enable 9 of flash chips of flash bus0,1 Test data output for JTAG Test reset for JTAG OTP mode select signal 1 OTP mode select signal 2 Ground Test data input for JTAG Test mode select for JTAG Test clock for JTAG Ground Data bus of PCMCIA Data bus of PCMCIA Data bus of PCMCIA Data bus of PCMCIA Data bus of PCMCIA Data bus of PCMCIA PCMCIA power IOIS16 of PCMCIA STSCHG of PCMCIA DASP for IDE REG of PCMCIA INPACK of PCMCIA Signal Name Pin Type I/O Type Function 8 S3C49F9X SOLID DISK CONTROLLER PIN INFORMATION Table 2-2 I/O Type Description I/O Type I1 I2 I3 I4 I5 I6 I7 O1 O2 O3 O4 O5 O6 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 OSC PVIL3 PVILU3 PIS PIC PICU PICD PVILD3 PVOB43 POD4 POB4 POB4SM POB16SM POB12 PVBTT43 PBCT4 PBCT4SM PBCUT4SM PBCT8SM PBCUT8SM PBCDT8 PBSDT4SM PBCT16SM PVBTD43 PSOSCM26 3.3V TTL schmitt trigger level PCMCIA LIN input buffer 3.3V TTL schmitt trigger level PCMCIA LIN input buffer with pull-up register CMOS schmitt trigger level input buffer CMOS level input buffer CMOS level input buffer with pull-up register CMOS level input buffer with pull-down register 3.3V TTL schmitt trigger level PCMCIA LIN input buffer with pull-down register 3.3V 4mA PCMCIA output buffer without SRC 4mA open drain output buffer 4mA Normal output buffer 4mA Normal output buffer with medium slew-rate control 16mA Normal output buffer with medium slew-rate control 12mA Normal output buffer 3.3V 4mA PCMCIA LIN bi-directional buffer without SRC CMOS level input buffer and 4mA tri-state output buffer CMOS level input buffer and 4mA tri-state output buffer with medium slew-rate control CMOS level input buffer with pull-up register and 4mA tri-state output buffer with medium slew-rate control CMOS level input buffer and 8mA tri-state output buffer with medium slew-rate control CMOS level input buffer with pull-up register and 8mA tri-state output buffer with medium slew-rate control CMOS level input buffer with pull-down register and 8mA tri-state output buffer CMOS schmitt trigger level input buffer with pull-down register and 4mA tri-state output buffer with medium slew-rate control CMOS level input buffer and 16mA tri-state output buffer with medium slew-rate control 3.3V 4mA PCMCIA LIN bi-directional buffer without SRC with pull-down register Oscillator cell with enable and register Pad Type Description 9 S3C49F9X SOLID DISK CONTROLLER PIN INFORMATION 2.3 Pin description for host interface Table 2-3 Pin description for host interface Signal Name XARD0 XARD1 XARD2 XARD3 XARD4 XARD5 XARD6 XARD7 XARD8 XARD9 XARD10 XDB0 XDB1 XDB2 XDB3 XDB4 XDB5 XDB6 XDB7 XDB8 XDB9 XDB10 XDB11 XDB12 XDB13 XDB14 XDB15 XREG 100-Pin Number 5 6 7 8 9 11 12 13 17 18 22 94 93 92 37 36 35 34 33 91 90 89 31 30 29 28 27 99 ATTRIBUTE MEMORY AREA SELECTION : This signal is used during memory cycles to distinguish between common memory and register (Attribute) memory accesses. High for Common memory, low for attribute memory. The signal must also be active (low) during I/O cycles when the I/O address is on I the Bus. In True IDE mode, this input signal is not used and should be connected to VCC by the host. I/O In True IDE mode, all Task File operations occur in byte mode on the low order bus XDB0-XDB7 while all data transfers are 16 bit using XDB0-XDB15. This signal is the same as the PC Card memory mode signal in PC Card I/O mode. DATA BUS[15:0] : These lines carry the Data, Commands and Status information between the host and the controller. XDB0 is the LSB of the even byte of the word. XDB8 is the LSB of the odd byte of the word. In True IDE Mode only A[2:0] are used to select the one of eight registers in the Task File, the remaining address lines should be grounded by the host. I This signal is the same as the PC Card Memory Mode signal in PC Card I/O mode. ADDRESS BUS[10:0] : These address lines along with the -REG signal are used to select the following: The I/O port address registers within the PC Storage Card, the memory mapped port address registers within the PC Storage Card, a byte in the Card's information structure and its configuration control and status registers. I/O Description 10 S3C49F9X SOLID DISK CONTROLLER PIN INFORMATION Table 2-3 Pin description for host interface(Cont.) Signal Name XCE1 100-Pin Number 23 I CARD ENABLE : These input signals are used both to select the card and to indicate to the card whether a byte or a word operation is being performed. -CE2 always accesses the odd byte of the word. -CE1 accesses the even byte or the Odd byte of the word depending on A0 and -CE2. A multi-plexing scheme based on A0, -CE1, -CE2 allows 8 bit hosts to access all data on XDB0-XDB7. See tables 3-7,3-8,4-3 and 4-4. This signal is the same as the PC card memory mode signal in PC Card I/O mode. In the True IDE mode, CS0 is the chip select for the task file registers while CS1 is used to select the alternate status register and the device control register. XCE2 XOE 24 21 I I OUTPUT ENABLE : This is an output enable strobe generated by the host interface. It is used to read data from the PC Card in memory mode and to read the CIS and configuration registers. In PC Card I/O mode, this signal is used to read the CIS and configuration registers. To enable True IDE mode this input should be grounded by the host. XWE 15 I WRITE ENABLE : This is a signal driven by the host and used for strobing memory write data to the registers of the PC Card when the card is configured in the memory interface mode. It is also used for writing the configuration registers. In PC Card I/O mode, this signal is used for writing the configuration registers. In True IDE mode, this input signal is not used and should be connected to VCC by the host. XWAIT 1 O WAIT : The -WAIT signal is driven low by the PC Card to signal the host to delay completion of a memory or I/O cycle that is in progress. IORDY : In True IDE mode, this output signal may be used as IORDY. I/O Description 11 S3C49F9X SOLID DISK CONTROLLER PIN INFORMATION Table 2-3 Pin description for host interface(Cont.) Signal Name XIOIS16 100-Pin Number 96 I/O I/O PORT IS 16 BITS : Memory mode - The PC Card does not have a write protect switch. This signal is held low after the completion of the reset initialization sequence. I/O operation - When the PC Card is configured for I/O operation pin 24 is used for the -I/O selected is 16-Bit Port (-IOIS16) function. A low signal indicates that a 16 bit or odd byte only operation can be performed at the addressed port. In True IDE mode, this output signal is asserted low when this device is expecting a word data transfer cycle. XINPACK 100 O INPUT PORT ACKNOWLEDGE : This signal is not used in memory mode. The Input acknowledge signal is asserted by the PC Card when the card is selected and responding to an I/O read cycle at the address that is on the address bus. This signal is used by the host to control the enable of any input data buffers between the PC Card and the CPU. In True IDE mode, this output signal is not used and should be connected at the host. XRDY/ 14 O READY/BUSY : In memory mode, this signal is set high when the PC Card is ready to accept a new data transfer operation and held low when the card is busy. The host memory card socket must provide a pull-up resistor. At power up and at reset, the RDY/-BSY signal is held low (busy) until the PC Card has completed its power up or reset function. No access of any type should be made to the PC Card during this time. The RDY/-BSY signal is held high (disabled from being busy) whenever the following condition is true: The PC Card has been powered up with +RESET continuously disconnected or asserted. I/O operation - After the PC Card has been configured for I/O operation, this signal is used as Interrupt request. This line is strobed low to generate a pulse mode interrupt or held low for a level mode interrupt. In True IDE mode, this signal is the active high Interrupt request to the host. I/O Description 12 S3C49F9X SOLID DISK CONTROLLER PIN INFORMATION Table 2-3 Pin description for host interface(Cont.) Signal Name XIORD 100-Pin Number 20 I I/O READ : This signal is not used in memory mode. This is an I/O read strobe generated by the host. This signal gates I/O data onto the bus from the PC Card when the card is configured to use the I/O interface. In True IDE Mode, this signal has the same function as in PC Card I/O Mode. XIOWR 19 I I/O WRITE : This signal is not used in memory mode. The I/O write strobe pulse is used to clock I/O data on the card data bus into the PC Card controller registers when the PC Card is configured to use the I/O interface. The clocking will occur on the negative to positive edge of the signal (trailing edge). In True IDE mode, this signal has the same function as in PC Card I/O Mode. XSTSCHG 97 I/O STATUS CHANGED : This signal is asserted high as the BVD1 signal since a battery is not used with this product. This signal is asserted low to alert the host to changes in the RDY/-BSY and write protect states, while the I/O interface is configured. Its use is controlled by the Card config and status In the True IDE mode, this input / output is the pass diagnostic signal in the Master / Slave handshake protocol. XDS 3 I CARD SELECT : In True IDE mode, this signal is used for configure this device as a master or slave. When it is grounded , the device is configured as a master. When this signal is open, the device is configured as a slave. In I/O and memory mode, this signal is not used. XRESET 2 I RESET : When the pin is high, this signal resets the PC Card. The PC Card is reset only at Power up if this pin is left high or open from power-up. The PC Card is also reset when the soft reset bit in the Card Configuration Option Register is set. In the True IDE mode, this input pin is the active low hardware reset from the host. I/O Description 13 S3C49F9X SOLID DISK CONTROLLER PIN INFORMATION Table 2-3 Pin description for host interface(Cont.) Signal Name XDASP 100-Pin Number 98 I/O This output line is always driven to a high state in memory mode since a battery is not required for this product. This output line is always driven to a high state in I/O mode since this product does not support the audio function. In the True IDE mode, this input/output is the disk active/slave present signal in the Master/Slave handshake protocol. XP55 XP56 VDEOT XTEST 52 75 I O O I Input for inverter Output for inverter Voltage detect output Test input for test mode I/O Description 14 S3C49F9X SOLID DISK CONTROLLER PIN INFORMATION 2.4 Pin Assignment for Flash Memory Interface Table 2-4 Pin description for Flash memory interface Signal Name FDB0 FDB1 FDB2 FDB3 FDB4 FDB5 FDB6 FDB7 FDB8 FDB9 FDB10 FDB11 FDB12 FDB13 FDB14 FDB15 FRDY0 FRDY1 FALE0 FALE1 100-Pin Number 50 53 54 55 57 58 59 60 44 48 42 I/O I I/O I/O FLASH READY 0/1 : The signal is used for indicate to the controller, which flash memory is ready to accept a command. FDB0 ~ FDB7 are controlled by FRDY0 signal, FDB8 ~ FDB15 are controlled by FRDY1. FLASH ADDRESS LATCH ENABLE 0/1 : When this signal is asserted the controller can send an address to the flash memory by asserting of FWE pin. FDB0 ~ FDB7 are controlled by FALE0 signal, FDB8 ~ FDB15 are controlled by FALE1. FCLE0 FCLE1 FRE0 FRE1 FWE0 FWE1 47 41 46 40 45 I/O I/O I/O I/O I/O O FLASH COMMAND LATCH ENABLE 0/1 : When this signal is asserted, a command can be to the flash memory. FDB0 ~ FDB7 are controlled by FCLE0 signal, FDB8 ~ FDB15 are controlled by FCLE1. FLASH READ ENABLE 0/1 : This signal is asserted to enable the reading of data from the flash memory. FDB0 ~ FDB7 are controlled by FRE0 signal, FDB8 ~ FDB15 are controlled by FRE1. FALSH WRITE ENABLE 0/1 : When this signal is asserted , the controller can write data to the flash memory. FDB0 ~ FDB7 are controlled by FWE0 signal, FDB8 ~ FDB15 are controlled by FWE1. I/O FLASH DATA BUS[15:0] : These lines are 16-bit data lines to/from the flash memory chip. I/O Description 15 S3C49F9X SOLID DISK CONTROLLER PIN INFORMATION Table 2-4 Pin description for Flash memory interface(Cont.) Signal Name FCE0 FCE1 FCE2 FCE3 FCE4 FCE5 FCE6 FCE7 FCE8 FCE9 FWP FPWR 100-Pin Number 65 66 67 68 69 70 71 77 78 79 72 73 I/O O Write protect of flash chips of flash bus 0, 1 Power control signal for flash memory I/O FLASH CHIP ENABLE [9:0] : These lines are flash memory enable signal. I/O Description 16 S3C49F9X SOLID DISK CONTROLLER PIN INFORMATION 2.5 Pin Assignment for external memory control Table 2-5 Pin description for external memory interface Signal Name ADDR0 ADDR1 ADDR2 ADDR3 ADDR4 ADDR5 ADDR6 ADDR7 ADDR8 ADDR9 ADDR10 ADDR11 ADDR12 ADDR13 ADDR14 ADDR15 ADDR16 DATA0 DATA1 DATA2 DATA3 DATA4 DATA5 DATA6 DATA7 nRCS nSCS nOE 100-Pin Number O O O EXTERNAL ROM CHIP SELECT : When this signal is asserted(low active) , the controller can access the external ROM device. EXTERNAL SRAM CHIP SELECT : When this signal is asserted(low active) , the controller can access the external SRAM device. OUTPUT ENABLE : This signal is data output enable signal. When an external memory access for ROM/SRAM occurs, this signal controls the output enable port of the specific device. nWE O WRITE ENABLE : When an external memory device access for SRAM/ROM occurs, this signal control the write enable port of the specific device. I/O EXTERNAL MEMORY DATA BUS [7:0] : These signals are data bus to access external memory device as SRAM or ROM. O EXTERNAL MEMORY ADDRESS BUS [16:0] : These signals are address bus to access external memory device as SRAM or ROM. I/O Description 17 S3C49F9X SOLID DISK CONTROLLER PIN INFORMATION Table 2-5 Pin description for external memory interface(Cont.) Signal Name TCK 100-Pin Number 87 I TEST CLOCK : The KS32P49F9X contains internally in-circuit emulation block for debugger mode which use standard JTAG protocol. When the controller go into debugger mode, this signal is provided from external debugger tool. TMS TDI nTRST TDO XI XO nRESET SW1 86 85 81 80 62 63 I I I I/O OC OC I I TEST MODE SELECT : In the debugger mode, this signal select test mode. This pin should be held to "1', when do not use the JTAG block. TEST DATA INPUT : In the debugger mode, this signal is used for carry data. from external debugger tool to the controller. TEST RESET : This signal should be sustained LOW first at the begging of normal operation. TEST DATA OUTPUT : In the debugger mode, this signal is used for carry data. from the controller to external debugger tool. INPUT CLOCK : This signal is system clock. OUTPUT CLOCK : RESET : This pin is system power on reset . A low input will stop all operation within the controller. ROM SELECTION : This pin is used for select ROM. When this signal set "1", the controller access external ROM. When this pin is "0", the controller access internal ROM. SW0 I FLASH NUMBER OF SELECTION : Basically flash memory can be connected up to 20. But if use the external buffer on pc card , flash memory can be connected up to 32. This signal is used for select number of flash. When this signal is high, can be connected up to 20. In the case of low, can be connected up to 32. CTEST 74 I CORE TEST : This signal is used for test CPU(ARM7TDMI) core. When this signal is low(0), the controller operate normal mode. When it is high(1), operate CPU test mode. CMODE I INTERRUPT ENABLE : This signal is used for control interrupt signal of CPU, when the signal is set(1), interrupt signal of CPU can be enabled. When this signal is cleared(0), interrupt signal can be disabled. TEST1 TEST2 82 83 I I OTP MODE SELECT : These signals are used for select OTP mode. When OTPMS1 and OTPMS2 are low, the controller operate normal mode. To operate the OTP mode, OTPMS1 and OTPMS2 signal should be set to low and high. The others setting mode are reserved for chip maker. I/O Description 18 S3C49F9X SOLID DISK CONTROLLER PIN INFORMATION 2.6 Power Pin Assignment Table 2-6 Pin description for power signal Signal Name VDD PVDD FVPP GND 4,16,26,43,51,56,76 32,95 38 25,39,49,61,64,84,88 System power supply voltage PCMCIA power supply voltage High voltage power for internal OTP(12.5V) Ground 100-Pin Number I/O Description 19 S3C49F9X SOLID DISK CONTROLLER INTERFACE BUS TIMMING 3 1. INTERFACE BUS TIMMING There are two types of bus cycles and timing sequences that occur in the PCMCIA type interface, a direct mapped I/O transfer and a memory access. The two timing sequences are explained in detail in the PCMCIA PC Card Standard. The PC Card conforms to the timing in that reference document. 3.1 Attribute Memory Read Timing Specification The attribute memory read time is defined as 300ns. Detailed timing specifications are shown in Table 3- Table 3-1 Attribute Memory Read Timing Parameter Symbol IEEE Symbol 300 ns Min ns. Read Cycle Time Address Access Time Card Enable Access Time Output Enable Access Time Output Disable Time from CE Output Disable Time from OE Address Setup Time Output Enable Time from CE Output Enable Time from OE Data Valid from Address Change Note. tcR ta(A) ta(CE) ta(OE) tdis(CE) tdis(OE) tsu(A) ten(CE) ten(OE) tv(A) TAVAV TAVQV TELQV TGLQV TEHQZ TGHQZ TAVWL TELQNZ TGLQNZ TAXQX 30 5 5 0 300 300 300 150 100 100 Max ns. All times are in nanosecond. Dout signifies data provided by the PC Card to the system. The -CE signal or both the -OE signal & the -WE signal must be de-asserted between consecutive cycle operation. 20 S3C49F9X SOLID DISK CONTROLLER INTERFACE BUS TIMMING tc(R) An -REG tsu(A) ta(A) tv(A) ta(CE) ten(CE) tdis(CE) ta(OE) ten(OE) tdis(OE) -CE -OE Dout . Figure 3-1 Attribute Memory Read Timing Diagram 21 S3C49F9X SOLID DISK CONTROLLER INTERFACE BUS TIMMING 3.2 Attribute Memory Write Timing Specification The attribute memory access time is defined as 250 ns. Detailed timing specifications are shown in table 3-2. Note. A host cannot write to CIS. This timing is specified only for the write to Configuration Register. Table 3-2 Attribute Memory Write Timing Parameter Symbol IEEE Symbol 250 ns Min ns. Write Cycle Time Write Pulse Width Address Setup Time Write Recovery Time Data Setup Time for WE Data Hold Time tcW tw(WE) tsu(A) trec(WE) tsu(D-WEH) th(D) tAVAV tWLWH tAVWL tWMAX tDVWH tWMDX 250 150 30 30 80 30 Max ns. Note. All times are in nanosecond. Din signifies data provided by the system to the PC Card. tc(W) -REG An tsu(A) trec(WE) tw(WE) tsu(D-WEH) th(D) -WE -CE -OE Din Data In Valid Figure 3-2 Attribute Memory Write Timing Diagram 22 S3C49F9X SOLID DISK CONTROLLER INTERFACE BUS TIMMING 3.3 Common Memory Read Timing Specification Table 3-3 Common Memory Read Timing Parameter Output Enable Access Time Output Disable Time from OE Address Setup Time Address Hold Time CE Setup before OE CE Hold following OE Wait Delay Falling from OE Data Setup for Wait Release Wait Width Time ta(OE) tdis(OE) tsu(A) th(A) tsu(CE) th(CE) tv(WT-OE) tv(WT) tw(WT) Symbol IEEE Symbol tGLQV tGHQZ tAVGL tGHAX tELGL tGHEH tGLWTV tQVWTH tWTLWTH 30 20 0 20 35 0 350 Min ns. Max ns. 125 100 Note. The maximum load on -WAIT is 1 LSTTL with 50pF total load. All times are in nanoseconds. Dout signifies data provided by the PC Card to the system. The -WAIT signal may be ignored if the -OE cycle to cycle time is greater than the Wait Width time. The Max Wait Width time can be determined from the Card Information Structure. The Wait Width time meets the PCMCIA specification of 12s but is intentionally less in this specification. An tsu(A) th(A) -REG -CE -OE tw(WT) tsu(CE) ta(OE) th(CE) -WAIT tv(WT-OE) tv(WT) tdis(OE) Dout Figure 3-3 Common Memory Read Timing Diagram 22 S3C49F9X SOLID DISK CONTROLLER INTERFACE BUS TIMMING 3.4 Common Memory Write Timing Specification Table 3-4 Common Memory Write Timing Parameter Data Setup before WE Data Hold following WE WE Pulse Width Address Setup Time CE Setup before WE Write recovery Time Address Hold Time CE Hold following WE Wait Delay Falling from WE WE High from Wait Release Wait Width Time Note. Symbol tsu(D-WEH) th(D) tw(WE) tsu(A) tsu(CE) trec(WE) th(A) th(CE) tv(WT-WE) tv(WT) tw(WT) IEEE Symbol tDVWH tlWMDX tWLWH tAVWL tELWL tWMAX tGHAX tGHEH tWLWTV tWTHWH tWTLWTH 0 350 Min ns. 80 30 150 30 0 30 20 20 35 Max ns. The maximum load on -WAIT is 1 LSTTL with 50pF total load. All times are in nanoseconds. Din signifies data provided by the system to the PC Card. The -WAIT signal may be ignored if the -WE cycle to cycle time is greater than the Wait Width time. The Max Wait Width time can be determined from the Card Information Structure. The Wait Width time meets the PCMCIA specification of 12s but is intentionally less in this specification. An tsu(A) th(A) th(CE) tw(WE) trec(WE) -REG -CE -WE tw(WT) tsu(CE) -WAIT tv(WT-WE) tsu(D-WEH) tv(WT) th(D) Din Din Valid Figure 3-4 Common Memory Write Timing Diagram 23 S3C49F9X SOLID DISK CONTROLLER INTERFACE BUS TIMMING 3.5 I/O Input (Read) Timing Specification Table 3-5 I/O Read Timing Parameter Data Delay after IORD Data Hold following IORD IORD Width Time Address Setup before IORD Address Hold following IORD CE Setup before IORD CE Hold following IORD REG Setup before IORD REG Hold following IORD INPACK Delay Falling from IORD INPACK Delay Rising from IORD IOIS16 Delay Falling from Address IOIS16 Delay Rising from Address Wait Delay Falling from IORD Data Delay from Wait Rising Wait Width Time Note. Symbol td(IORD) th(IORD) tw(IORD) tsuA(IORD) thA(IORD) tsuCE(IORD) thCE(IORD) tsuREG(IORD) thREG(IORD) tdfINPACK(IORD) tdrINPACK(IORD) tdfIOIS16(ADR) tdrIOIS16(ADR) tdWT(IORD) td(WT) tw(WT) IEEE Symbol tlGLQV tlGHQX tlGLIGH tAVIGL tlGHAX tELIGL tlGHEH tRGLIGL tlGHRGH tlGLIAL tlGHIAH tAVISL tAVISH tlGLWTL tWTHQV tWTLWTH 0 165 70 20 5 20 5 0 0 45 45 35 35 35 0 350 Min ns. Max ns. 100 The maximum load on -WAIT, -INPACK and -IOIS16 is 1 LSTTL with 50pF total load. All times are in nanoseconds. Minimum time from -WAIT high to -IORD high is 0nsec, but minimum -IORD width must still be met. Dout signifies data provided by the PC Card to the system. The Wait Width time meets the PCMCIA specification of 12s but is intentionally less in this specification. An -REG -CE -IORD -INPACK tdfIOIS16(ADR) -IOIS16 -WAIT tdWT(IORD) tsu(IORD) tsuREG(IORD) tsuCE(IORD) twIORD tdfINPACK(IORD) td(IORD) td(WT) tw(WT) th(IORD) tdrINPACK(IORD) tdrIOIS16(ADR) thA(IORD) thREG(IORD) thCE(IORD) Dout Figure 3-5 I/O Read Timing Diagram 24 S3C49F9X SOLID DISK CONTROLLER INTERFACE BUS TIMMING 3.6 I/O Output (Write) Timing Specification Table 3-6 I/O Write Timing Parameter Data Setup before IOWR Data Hold following IOWR IOWR Width Time Address Setup before IOWR Address Hold following IOWR CE Setup before IOWR CE Hold following IOWR REG Setup before IOWR REG Hold following IOWR IOIS16 Delay Falling from Address IOIS16 Delay Rising from Address Wait Delay Falling from IOWR IOWR high from Wait high Wait Width Time Note. Symbol tsu(IOWR) th(IOWR) twIOWR tsuA(IOWR) thA(IOWR) tsuCE(IOWR) thCE(IOWR) tsuREG(IOWR) thREG(IOWR) tdfIOIS16(ADR) tdrIOIS16(ADR) tdWT(IOWR) tdrIOWR(WT) tw(WT) IEEE Symbol tDVIWH tlWHDX tlWLIWH tAVIWL tlWHAX tELIWL tlWHEH tRGLIWL tlWHRGH tAVISL tAVISH tlWLWTL tWTJIWH tWTLWTH 0 350 Min ns. 60 30 165 70 20 5 20 5 0 35 35 35 Max ns. The maximum load on -WAIT, -INPACK, and -IOIS16 is 1 LSTTL with 50pF total load. All times are in nanoseconds. Minimum time from -WAIT high to -IOWR high is 0nsec, but minimum -IOWR width must still be met. Din signifies data provided by the system to the PC Card. The Wait Width time meets the PCMCIA specification of 12s but is intentionally less in this specification. An -REG -CE -IOWR -IOIS16 tdfIOIS16(ADR) tsu(IOWR) tsuREG(IOWR) tsuCE(IOWR) twIORD tsu(IOWR) tw(WT) th(IOWR) tdrIOWR(WT) Din Valid thA(IOWR) thREG(IOWR) thCE(IOWR) tdrIOIS16(ADR) -WAIT tdWT(IOWR) Din Figure 3-6 I/O Write Timing Diagram 25 S3C49F9X SOLID DISK CONTROLLER INTERFACE BUS TIMMING 3.7 IDE Mode I/O Input(Read) Timing Specification Table 3-7 IDE Mode I/O Read Timing Parameter Data Delay after IORD Data Hold following IORD IORD Width Time Address Setup before IORD Address Hold following IORD CE Setup before IORD CE Hold following IORD IOIS16 Delay Falling from Address IOIS16 Delay Rising from Address Symbol td(IORD) th(IORD) tw(IORD) tsuA(IORD) thA(IORD) tsuCE(IORD) thCE(IORD) tdfIOIS16(ADR) tdrIOIS16(ADR) IEEE Symbol tlGLQV tlGHQX tlGLIGH tAVIGL tlGHAX tELIGL tlGHEH tAVISL tAVISH 0 165 70 20 5 20 35 35 Min ns. Max ns. 100 Note. The maximum load on -IOIS16 is 1 LSTTL with 50pF total load. All times are in nanoseconds. Minimum time from -WAIT high to -IORD high is 0nsec, but minimum -IORD width must still be met. Dout signifies data provided by the PC Card to the system. An -CE -IORD -IOIS16 tdfIOIS16(ADR) th(IORD) tsuA(IORD) tsuCE(IORD) twIORD td(IORD) tdrIOIS16(ADR) thA(IORD) thCE(IORD) Dout Figure 3-7 IDE Mode I/O Read Timing Diagram 26 S3C49F9X SOLID DISK CONTROLLER INTERFACE BUS TIMMING 3.8 IDE Mode I/O Output(Write) Timing Specification Table 3-8 IDE Mode I/O Write Timing Parameter Data Setup before IOWR Data Hold following IOWR IOWR Width Time Address Setup before IOWR Address Hold following IOWR CE Setup before IOWR CE Hold following IOWR IOIS16 Delay Falling from Address IOIS16 Delay Rising from Address Symbol tsu(IOWR) th(IOWR) twIOWR tsuA(IOWR) thA(IOWR) tsuCE(IOWR) thCE(IOWR) tdfIOIS16(ADR) tdrIOIS16(ADR) IEEE Symbol tDVIWH tlWHDX tlWLIWH tAVIWL tlWHAX tELIWL tlWHEH tAVISL tAVISH Min ns. 60 30 165 70 20 5 20 35 35 Max ns. Note. The maximum load on -IOIS16 is 1 LSTTL with 50pF total load. All times are in nanoseconds. Minimum time from -WAIT high to -IOWR high is 0nsec, but minimum -IOWR width must still be met. Din signifies data provided by the system to the PC Card. An -CE -IOWR -IOIS16 tdfIOIS16(ADR) tsu(IOWR) Din Valid th(IOWR) tsuA(IOWR) tsuCE(IOWR) twIOWR tdrIOIS16(ADR) thA(IOWR) thCE(IOWR) Din Figure 3-8 I/O Write Timing Diagram 27 S3C49F9X SOLID DISK CONTROLLER CARD CONFIGURATION 4 use in I/O cards. CARD CONFIGURATION The PC Cards are identified by appropriate information in the Card Information Structure (CIS). The following configuration registers are used to coordinate the I/O spaces and the Interrupt level of cards that are located in the system. In addition, these registers provide a method for accessing status information about the PC Card that may be used to arbitrate between multiple interrupt sources on the same interrupt level or to replace status information that appears on dedicated pins in memory cards that have alternate Table 4-1 Registers and Memory Space Decoding -CE2 -CE1 1 x 1 0 0 x 1 0 0 x 1 1 1 0 0 1 0 0 1 0 0 0 1 0 0 0 0 0 1 1 -REG x 0 1 1 1 0 1 1 1 0 0 0 0 0 0 -OE x 0 0 0 0 1 1 1 1 0 1 0 1 0 1 -WE x 1 1 1 1 0 0 0 0 1 0 1 0 1 0 A10 A9 A8-A4 A3 A2 A1 A0 x x x x x x x x x 0 0 x x x x x 1 x x x 1 x x x 0 0 x x x x xx xx xx xx xx xx xx xx xx xx xx xx xx xx xx x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x Standby 0 Configuration Registers Read x Common Memory Read(8bit D7-D0) x Common Memory Read(8bit D15-D8) 0 Common Memory Read(16bit D15-D0) 0 Configuration Registers Write x Common Memory Write(8bit D7-D0) x Common Memory Write(8bit D15-D8) 0 Common Memory Write(16bit D15-D0) 0 Card Information Structure Read 0 Invalid Access (CIS Write) 1 Invalid Access (Odd Attribute Read) 1 Invalid Access (Odd Attribute Write) x Invalid Access (Odd Attribute Read) x Invalid Access (Odd Attribute Write) SELECTED SPACE 28 S3C49F9X SOLID DISK CONTROLLER CARD CONFIGURATION Table 4-2 Configuration Registers Decoding -CE2 -CE1 x x x x x x x x Note. 0 0 0 0 0 0 0 0 -REG 0 0 0 0 0 0 0 0 -OE 0 1 0 1 0 1 0 1 -WE 1 0 1 0 1 0 1 0 A10 A9 A8-A4 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 00 00 00 00 00 00 00 00 A3 0 0 0 0 0 0 0 0 A2 A1 A0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 SELECTED SPACE 0 Configuration Option Reg Read 0 Configuration Option Reg Write 0 Card Status Register Read 0 Card Status Register Write 0 Pin Replacement Register Read 0 Pin Replacement Register Write 0 Socket and Copy Register Read 0 Socket and Copy Register Write The location of the card configuration registers should always be read from the CIS since these locations may vary in future products. No writes should be performed to the PC Card attribute memory except to the card configuration register addresses. All other attribute memory locations are reserved. 29 S3C49F9X SOLID DISK CONTROLLER CARD CONFIGURATION 4.1 Attribute Memory Function Attribute memory is a space where PC Card identification and configuration information are stored, and is limited to 8-bit wide accesses only at even addresses. The card configuration registers are also located here. For the attribute memory read function, signals -REG and -OE must be active and -WE inactive during the cycle. As in the main memory read functions, the signals -CE1 and -CE2 control the even-byte and odd-byte address, but only the even-byte data is valid during the attribute memory access. Refer to table 4-3 below for signal states and bus validity for the attribute memory function. Table 4-3 Attribute Memory Function Function Mode Standby Mode Read Byte Access CIS (8 bits) Write Byte Access CIS (8 bits) (invalid) Read Byte Access Configuration (8 bits) Write Byte Access Configuration (8 bits) Read Word Access CIS (16 bits) Write Word Access CIS (16 bits) (invalid) Read Word Access Configuration (16 bits) Write Word Access Configuration (16 bits) Note The -CE signal or both the -OE signal and the -WE signal must be de-asserted between consecutive cycle operations. L L L H x H L Don't Care Even Byte L L L H x L H Not Valid Even Byte L L L L x H L Don't Care Even Byte L L L L x L H Not Valid Even Byte L H L H L H L Don't Care Even Byte L H L H L L H High Z Even Byte L H L L L H L Don't Care Even Byte -REG -CE2 -CE1 x L H H H L A9 x L A0 x L -OE x L -WE x H D15-D8 High Z High Z D7-D0 High Z Even Byte 30 S3C49F9X SOLID DISK CONTROLLER CARD CONFIGURATION 4.2 Configuration Option Register (Address 200h in attribute memory) The Configuration Option Register is used to configure the cards interface, address decoding and interrupt and to issue a soft reset to the PC Card. Operation R/W SRESET D7 SRESET D6 LevIREQ D5 Conf5 D4 Conf4 D3 Conf3 D2 Conf2 D1 Conf1 D0 Conf0 Soft Reset - Setting this bit to one (1), waiting the minimum reset width time and returning to zero (0) places the PC Card in the reset state. Setting this bit to one (1) is equivalent to assertion of the +RESET signal except that the SRESET bit is not cleared. Returning this bit to zero (0) leaves the PC Card in the same un-configured, Reset state as following power-up and hardware reset. This bit is set to zero (0) by power-up and hardware reset. Using the PCMCIA Soft Reset is considered a hardware reset by the ATA commands. Contrast with software reset in the Device Control Register. LevIREQ This bit is set to one (1) when Level Mode Interrupt is selected, and zero (0) when pulse mode is selected. Set to zero (0) by reset. Conf5 - Conf0 Note: Configuration Index. Set to zero (0) by reset. It's used to select operation mode of the PC Card as shown below. Conf5 and Conf4 are reserved and must be written as zero (0) Table 4-4 Card Configurations Conf5 0 0 0 0 Conf4 0 0 0 0 Conf3 0 0 0 0 Conf2 0 0 0 0 Conf1 0 0 1 1 Conf0 0 1 0 1 Disk Card Mode Memory Mapped I/O Mapped, Any 16byte system decoded boundary I/O Mapped, 1F0-1F7/3F6-3F7 I/O Mapped, 170-177/376-377 31 S3C49F9X SOLID DISK CONTROLLER CARD CONFIGURATION 4.3 Card Configuration and Status Register (Address 202h in attribute memory) The Card Configuration and Status Register contains information about the Card's condition. Operation Read Write D7 Changed 0 D6 SigChg SigChg D5 IOis8 IOis8 D4 0 0 D3 0 0 D2 PwrDwn PwrDwn D1 Int 0 D0 0 0 Changed Indicates that one or both of the Pin Replacement register CRdy, or CWProt bits are set to one (1). When the Changed bit is set, -STSCHG Pin 46 is held low if the SigChg bit is a One (1) and the PC Card is configured for the I/O interface. SigChg This bit is set and reset by the host to enable and disable a state-change signal from the Status Register, the Changed bit control pin 46 the Changed Status signal. If no state change signal is desired, this bit should be set to zero (0) and pin 46 (-STSCHG) signal will be held high while the PC Card is configured for I/O. IOis8 The host sets this bit to a one (1) if the PC Card is to be configured in an 8 bit I/O Mode. The PC Card is always configured for both 8- and 16-bit I/O, so this bit is ignored. PwrDwn This bit indicates whether the host requests the PC Card to be in the power saving or active mode. When the bit is one (1), the PC Card enters a power down mode. When zero (0), the host is requesting the PC Card to enter the active mode. The PCMCIA Rdy/-Bsy value becomes BUSY when this bit is changed. Rdy/-Bsy will not become Ready until the power state requested has been entered. The PC Card automatically powers down when it is idle and powers back up when it receives a command. Int This bit represents the internal state of the interrupt request. This value is available whether or not I/O interface has been configured. This signal remains true until the condition which caused the interrupt request has been serviced. If interrupts are disabled by the -IEN bit in the Device Control Register, this bit is a zero (0). 32 S3C49F9X SOLID DISK CONTROLLER CARD CONFIGURATION 4.4 Pin Replacement Register (Address 204h in attribute memory) Operation Read Write D7 0 0 D6 0 0 D5 CRdy/-Bsy CRdy/-Bsy D4 CWProt CWProt D3 0 0 D2 0 0 D1 Rdy/-Bsy MRdy/-Bsy D0 WProt MWProt CRdy/-Bsy written by the host. CWProt by the host. Rdy/-Bsy This bit is set to one (1) when the bit RRdy/-Bsy changes state. This bit can also be This bit is set to one (1) when the RWprot changes state. This bit may also be written This bit is used to determine the internal state of the Rdy/-Bsy signal. This bit may be used to determine the state of the Ready/-Busy as this pin has been reallocated for use as Interrupt Request on an I/O card. When written, this bit acts as a mask for writing the corresponding bit CRdy/-Bsy. WProt This bit is always zero (0) since the PC Card does not have a Write Protect switch. When written, this bit acts as a mask for writing the corresponding bit CWProt. MRdy/-Bsy MWProt This bit acts as a mask for writing the corresponding bit CRdy/-Bsy. This bit when written acts as a mask for writing the corresponding bit CWProt. Table 4-5 Pin Replacement Changed Bit/Mask Bit Values Initial Value of (C) Status 0 1 x x Written by Host "C" Bit x x 0 1 "M" Bit 0 0 1 1 Final "C" Bit 0 1 0 1 Unchanged Unchanged Cleared by Host Set by Host Command 33 S3C49F9X SOLID DISK CONTROLLER CARD CONFIGURATION 4.5 Socket and Copy Register (Address 206h in attribute memory) This register contains additional configuration information. This register is always written by the system before writing the card's Configuration Index Register. Operation Read Write D7 Reserved 0 D6 0 0 D5 0 0 D4 Drive# Drive# D3 0 x D2 0 x D1 0 x D0 0 x Reserved This bit is reserved for future standardization. This bit must be set to zero (0) by the software when the register is written. Drive # This bit indicates the drive number of the card for twin card configuration. X The socket number is ignored by the PC Card. 34 S3C49F9X SOLID DISK CONTROLLER CARD CONFIGURATION 4.6 I/O Transfer Function 4.6.1 I/O Function The I/O transfer to or from the PC Card can be either 8 or 16 bits. When a 16-bit accessible port is addressed, the signal -IOIS16 is asserted by the PC Card. Otherwise, the -IOIS16 signal is de-asserted. When a 16 bit transfer is attempted, and the -IOIS16 signal is not asserted by the PC Card, the system must generate a pair of 8-bit references to access the word's even byte and odd byte. The PC Card permits both 8 and 16 bit accesses to all of its I/O addresses, so -IOIS16 is asserted for all addresses to which the PC Card responds. The PC Card may request the host to extend the length of an input cycle until data is ready by asserting the -WAIT signal at the start of the cycle. Table 4-6 I/O Function Function Mode Standby Mode Byte Input Access (8 bits) Byte Output Access (8 bits) Word Input Access (16 bits) Word Output Access (16 bits) I/O Read Inhibit I/O Write Inhibit High Byte Inout Only (8 bits) High Byte Output Only (8 bits) L L H x H L Odd Byte Don't Care H H L x x L x x H x x x L H L H L H Don't Care High Z Odd Byte Don't Care High Z High Z L L L L H L Odd Byte Even Byte -REG -CE2 -CE1 x L L L L L H H H H H L H L L L L L A0 x L H L H L -IORD x L L H H L -IOWR x H H L L H D15-D8 High Z High Z High Z Don't Care Don't Card Odd Byte D7-D0 High Z Even Byte Odd Byte Even Byte Odd Byte Even Byte 35 S3C49F9X SOLID DISK CONTROLLER CARD CONFIGURATION 4.7 Common Memory Transfer Function 4.7.1 Common Memory Function The common memory transfer to or from the PC Card can be either 8 or 16 bits. The PC Card permits both 8 and 16 bit accesses to all of its common memory addresses. The PC Card may request the host to extend the length of a memory write cycle or extend the length of a memory read cycle until data is ready by asserting the -WAIT signal at the start of the cycle. Table 4-7 Common Memory Function Function Mode Standby Mode Byte Read Access (8 bits) Byte Write Access (8 bits) Word Read Access (16 bits) Word Write Access (16 bits) Odd Byte Read Only (8 bits) Odd Byte Write Only (8 bits) H L H x H L Odd Byte Don't Care H L H x L H Odd Byte High Z H L L x H L Odd Byte Even Byte -REG -CE2 -CE1 x H H H H H H H H H H L H L L L L L A0 x L H L H x -OE x L L H H L -WE x H H L L H D15-D8 High Z High Z High Z Don't Care Don't Care Odd Byte D7-D0 High Z Even Byte Odd Byte Even Byte Odd Byte Even Byte 36 S3C49F9X SOLID DISK CONTROLLER CARD CONFIGURATION 4.8 IDE Mode I/O Transfer Function 4.8.1 IDE I/O Function The PC Card can be configured in a True IDE Mode of operation. The PC Card is configured in this mode only when the -OE input signal is grounded by the host during the power off to power on cycle. In this True IDE Mode the PCMCIA protocol and configuration are disabled and only I/O operations to the Task File and Data Register are allowed. In this mode no Memory or Attribute Registers are accessible to the host. Note: Removing and reinserting the PC Card while the host computer's power is on will reconfigure the PC Card to PC Card ATA mode from the original True IDE Mode. To configure the PC Card in True IDE Mode, the 50-pin socket must be power cycled with the PC Card inserted and -OE (output enable) asserted. The following table defines the function of the operations for the True IDE Mode. Table 4-8 IDE Mode I/O Function Function Mode Invalid Mode Standby Mode Task File Write Task File Read Data Register Write Data Register Read Control Register Write All Status Read -CE2 -CE1 L H H H H H L L L H L L L L H H A0 x x 1-7h 1-7h 0 0 6h 6h -IORD x x H L H L H L -IOWR x x L H L H L H D15-D8 High Z High Z Don't Care High Z Odd Byte in Odd Byte out Don't Care High Z D7-D0 High Z High Z Data In Data Out Even Byte in Even Byte out Control In Status Out 37 S3C49F9X SOLID DISK CONTROLLER CARD CONFIGURATION 4.9 ATA Drive Register Set Definition and Protocol The PC Card can be configured as a high performance I/O device through: a. Standard PC-AT disk I/O address spaces 1F0h-1F7h, 3F6h-3F7h (primary); 170h-177h, 376h377h(secondary) with IRQ 14 (or other available IRQ). b. Any system decoded 16 byte I/O block using any available IRQ. c. Memory space. The communication to or from the PC Card is done using the Task File registers which provide all the necessary registers for control and status information. The PCMCIA interface connects peripherals to the host using four register mapping methods. The following is a detailed description of these methods: Table 4-9 I/O Configurations Standard Configurations Config Index 0&8 1&9 2 & Ah 2 &Ah 3 & Bh 3 & Bh Note: I/O or Memory Memory I/O I/O I/O I/O I/O 0-F, 400-7FF xx0-xxF 1F0-1F7, 3F6-3F7 1F0-1F7, 3F6-3F7 170-177, 376-377 170-177, 376-377 0 0 0 1 0 1 Memory Mapped I/O Mapped 16 Contiguous Registers Primary I/O Mapped Drive 0 Primary I/O Mapped Drive 1 Secondary I/O Mapped Drive 0 Secondary I/O Mapped Drive 1 Address Drive # Description Refer to Section 4.5 for Twin Card implementation. 38 S3C49F9X SOLID DISK CONTROLLER CARD CONFIGURATION 4.9.1 I/O Primary and Secondary address configurations Table 4-10 Primary and Secondary I/O Decoding -REG 0 0 0 0 0 0 0 0 0 0 Note: A9-A4 1F(17) 1F(17) 1F(17) 1F(17) 1F(17) 1F(17) 1F(17) 1F(17) 3F(37) 3F(37) A3 0 0 0 0 0 0 0 0 0 0 A2 0 0 0 0 1 1 1 1 1 1 A1 0 0 1 1 0 0 1 1 1 1 A0 0 1 0 1 0 1 0 1 0 1 -IORD=0 Even RD Data Error Register Sector Count Sector No. Cylinder Low Cylinder High Select Card/Head Status Alt Status Drive Address -IOWR=0 Even WR Data Features Sector Count Sector No. Cylinder Low Cylinder High Select Card/Head Command Drive Control Reserved Notes 1,2 1 1. Register 0 is accessed with -CE1 low and -CE2 low (and A0 = Don't Care) as a word register on the combined Odd Data Bus and Even Data Bus (D15-D0). This register may also be accessed by a pair of byte accesses to the offset 0 with -CE1 low and -CE2 high. Note that the address space of this word register overlaps the address space of the Error and Feature byte-wide registers which lie at offset 1. When accessed twice as byte register with -CE1 low, the first byte to be accessed is the even byte of the word and the second byte accessed is the odd byte of the equivalent word access. 2. A byte accesses to register 0 with -CE1 high and -CE2 low accesses the error (read) or feature (write) register. 3. Address lines which are not indicated are ignored by the PC Card for accessing all the registers in this table. 39 S3C49F9X SOLID DISK CONTROLLER CARD CONFIGURATION 4.9.2 Configurations I/O Mapped Addressing When the system decodes a contiguous block of I/O registers to select the PC Card, the registers are accessed in the block of I/O space decoded by the system as follows: Table 4-11 Contiguous I/O Decoding -REG 0 0 0 0 0 0 0 0 0 0 0 0 0 Note: 1. Register 0 is accessed with -CE1 low and -CE2 low (and A0 = Don't Care) as a word register on the combined Odd Data Bus and Even Data Bus (D15-D0). This register may also be accessed by a pair of byte accesses to the offset 0 with -CE1 low and -CE2 high. Note that the address space of this word register overlaps the address space of the Error and Feature byte-wide registers that lie at offset 1. When accessed twice as byte register with -CE1 low, the first byte to be accessed is the even byte of the word and the second byte accessed is the odd byte of the equivalent word access. A byte access to register 0 with -CE1 high and -CE2 low accesses the error (read) or feature (write) register. 2. Registers at offset 8, 9 and D are non-overlapping duplicates of the registers at offset 0 and 1. Register 8 is equivalent to register 0, while register 9 accesses the odd byte. Therefore, if the registers are byte accessed in the order 9 then 8 the data will be transferred odd byte then even byte. Repeated byte accesses to register 8 or 0 will access consecutive (even than odd) bytes from the data buffer. Repeated word accesses to register 8, 9 or 0 will access consecutive words from the data buffer. Repeated byte accesses to register 9 are not supported. However, repeated alternating byte accesses to registers 8 then 9 will access consecutive (even then odd) bytes from the data buffer. Byte accesses to register 9 access only the odd byte of the data. 3. Address lines which are not indicated are ignored by the PC Card for accessing all the registers in this table. A3 A2 A1 A0 0 0 0 0 0 0 0 0 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 1 0 0 1 1 0 0 1 1 0 0 0 1 1 0 1 0 1 0 1 0 1 0 1 1 0 1 Offset 0 1 2 3 4 5 6 7 8 9 D E F -IORD=0 Even RD Data Error Sector Count Sector No. Cylinder Low Cylinder High Select Card/Head Status Dup. Even RD Data Dup. Odd RD Data Dup. Error Alt Status Drive Address -IOWR=0 Even WR Data Features Sector Count Sector No. Cylinder Low Cylinder High Select Card/Head Command Dup. Even WR Data Dup. Odd WR Data Dup. Feature Device Ctl Reserved 2 2 2 Notes 1 2 40 S3C49F9X SOLID DISK CONTROLLER CARD CONFIGURATION 4.9.3 Memory Mapped Addressing When the PC Card registers are accessed via memory references, the registers appear in the common memory space window: 0-2K bytes as follows: Table 4-12 Memory Mapped Decoding -REG A10 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Notes: 1. Register 0 is accessed with -CE1 low and -CE2 low as a word register on the combined Odd Data Bus and Even Data Bus (D15-D0). This register may also be accessed by a pair of byte accesses to the offset 0 with -CE1 low and -CE2 high. Note that the address space of this word register overlaps the address space of the Error and Feature byte-wide registers that lie at offset 1. When accessed twice as byte register with -CE1 low, the first byte to be accessed is the even byte of the word and the second byte accessed is the odd byte of the equivalent word access. A byte access to address 0 with -CE1 high and -CE2 low accesses the error (read) or feature (write) register. 2. Registers at offset 8, 9 and D are non-overlapping duplicates of the registers at offset 0 and 1. Register 8 is equivalent to register 0, while register 9 accesses the odd byte. Therefore, if the registers are byte accessed in the order 9 then 8 the data will be transferred odd byte then even byte. Repeated byte accesses to register 8 or 0 will access consecutive (even then odd) bytes from the data buffer. Repeated word accesses to register 8, 9 or 0 will access consecutive words from the data buffer. Repeated byte accesses to register 9 are not supported. However, repeated alternating byte accesses to registers 8 then 9 will access consecutive (even then odd) bytes from the data buffer. Byte accesses to register 9 access only the odd byte of the data. 3. Accesses to even addresses between 400h and 7FFh access register 8. Accesses to odd addresses between 400h and 7FFh access register 9. This 1Kbyte memory window to the data register is provided so that hosts can perform memory to memory block moves to the data register when the register lies in memory space. Some hosts, such as the X86 processors, must increment both the source and destination addresses when executing the memory to memory block move instruction. Some PCMCIA socket adapters also have auto incrementing address logic 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 A9-A4 x x x x x x x x x x x x x x x A3 A2 A1 A0 0 0 0 0 0 0 0 0 1 1 1 1 1 x x 0 0 0 0 1 1 1 1 0 0 1 1 1 x x 0 0 1 1 0 0 1 1 0 0 0 1 1 x x 0 1 0 1 0 1 0 1 0 1 1 0 1 0 1 Offset 0 1 2 3 4 5 6 7 8 9 D E F 8 9 -IORD=0 Even RD Data Error Sector Count Sector No. Cylinder Low Cylinder High Select Card/Head Status Dup. Even RD Data Dup. Odd RD Data Dup. Error Alt Status Drive Address Even RD Data Odd RD Data -IOWR=0 Even WR Data Features Sector Count Sector No. Cylinder Low Cylinder High Select Card/Head Command Dup. Even WR Data Dup. Odd WR Data Dup. Feature Device Ctl Reserved Even WR Data Odd WR Data 3 3 2 2 2 Notes 1 2 41 S3C49F9X SOLID DISK CONTROLLER CARD CONFIGURATION embedded within them. This address window allows these hosts and adapters to function efficiently. Note that this entire window accesses the Data Register FIFO and does not allow random access to the data buffer within the PC Card. A word access to address at offset 8 will provide even data on the low-order byte of the data bus, along with odd data at offset 9 on the high-order byte of the data bus. 4.9.4 True IDE Mode Addressing When the PC Card is configured in the True IDE Mode, the I/O decoding is as follows: Table 4-13 True IDE Mode I/O Decoding -CE2 1 1 1 1 1 1 1 1 0 0 -CE1 0 0 0 0 0 0 0 0 1 1 A2 0 0 0 0 1 1 1 1 1 1 A1 0 0 1 1 0 0 1 1 1 1 A0 0 1 0 1 0 1 0 1 0 1 -IORD=0 Even RD Data Error Sector Count Sector No. Cylinder Low Cylinder High Select Card/Head Status Alt Status Drive Address -IOWR=0 Even WR Data Features Sector Count Sector No. Cylinder Low Cylinder High Select Card/Head Command Device Control Reserved Notes 42 S3C49F9X SOLID DISK CONTROLLER CARD CONFIGURATION 4.10 ATA Registers The following section describes the hardware registers used by the host software to issue commands to the CompactFlash device. These registers are often collectively referred to as the "task file." Note: In accordance with the PCMCIA specification: each of the registers below which is located at an odd offset address may be accessed at its normal address and also the corresponding even address (normal address -1) using data bus lines (D15-D8) when -CE1 is high and -CE2 is low unless -IOIS16is high (not asserted) and an I/O cycle is being performed. 4.10.1 Data Register (Address -1F0[170]; Offset 0,8,9): The Data Register is a 16bit register, and it used to transfer data blocks between the PC Card data buffer and the Host. This register overlaps the Error Register. The table below describes the combinations of data register access and is provided to assist in understanding the overlapped Data Register and Error/Feature Register rather than to attempt Release 3.0 for definitions of the Card Accessing Modes for I/O and Memory cycles. Note: Because of the overlapped register, access to the 1f1h, 171h or offset 1 are not defined for word (-CE2 = 0 and - CE1 = 0) operations. These accesses are treated as accesses to the Word Data Register. The duplicated registers at offsets 8,9 and Dh have no restrictions on the operations that can be performed by the socket. to define general PCMCIA word and byte access modes and operations. See the PCMCIA PC Card Standard Data Register Word Data Register Even Data Register Odd Data Register Odd Data Register Error / Feature Register Error / Feature Register Error / Feature Register -CE2 0 1 1 0 1 0 0 -CE1 0 0 0 1 0 1 0 A0 x 0 1 x 1 x x Offset 0,8,9 0,8 9 8,9 1,Dh 1 Dh Data Bus D15-D0 D7-D0 D7-D0 D15-D8 D7-D0 D15-D8 D15-D8 43 S3C49F9X SOLID DISK CONTROLLER CARD CONFIGURATION 4.10.2 Error Register (Address -1F1[171]; Offset 1, Dh Read Only) This register contains additional information about the source of an error when an error is indicated in bit 0 of the Status register. The bits are defined as follows: D7 BBK D6 UNC D5 0 D4 IDNF D3 0 D2 ABRT D1 0 D0 AMNF This register is also accessed on data bits D15 -D8 during a write operation to offset 0 with -CE2 low and -CE1 high. Bit 7 (BBK) This bit is set when a Bad Block is detected.This bit is set when Error on drive 1 (True IDE). Bit 6 (UNC) Bit 5 Bit 4 (IDNF) Bit 3 Bit 2 (Abort) This bit is set when an Uncorrectable Read Error is encountered. This bit is 0. The requested sector ID is in error or cannot be found. This bit is 0 This bit is 0. Abort=1 This bit is set if the command has been aborted because of a CompactFlash Storage Card status condition (Write Fault, Invalid Parameter, etc) or when an invalid command has been issued. Bit 1 Bit 0 (AMNF) This bit is 0. This bit is set in case of a general error. (DMA transfer Error) 44 S3C49F9X SOLID DISK CONTROLLER CARD CONFIGURATION 4.10.3 Feature Register (Address -1F1[171]; Offset 1, Dh Write Only): This register provides information regarding features of the PC Card that the host can utilize. This register is also accessed on data bits D15-D8 during a write operation to Offset 0 with -CE2 low and -CE1 high. 4.10.4 Sector Count Register (Address -1F2[172]; Offset 2): This register contains the numbers of sectors of data requested to be transferred on a read or write operation between the host and the PC Card. If the value in this register is zero, a count of 256 sectors is specified. If the command was successful, this register is zero at command completion. If not successfully completed, the register contains the number of sectors that need to be transferred in order to complete the request 4.10.5 Sector Number (LBA 7-0) Register (Address -1F3[173]; Offset 3): This register contains starting sector number or bits 7-0 of the Logical Block Address (LBA) for any PC Card data access for the subsequent command. 4.10.6 Cylinder Low (LBA 15-8) Register (Address -1F4[174]; Offset 4): This register contains the low order 8 bits of the starting cylinder address or bits 15-8 of the Logical Block Address. 4.10.7 Cylinder High (LBA 23-16) Register (Address -1F5[175]; Offset 5): This register contains the high order 8 bits of the starting cylinder address or bits 23-16 of the Logical Block Address. 45 S3C49F9X SOLID DISK CONTROLLER CARD CONFIGURATION 4.10.8 Drive/Head (LBA 27-24) Register (Address -1F6[176]; Offset 6): The Drive/Head register is used to select the drive and head. It is also used to select LBA addressing instead of cylinder/head/sector addressing. The bits are defines as follows: D7 1 Bit 7 Bit 6 (LBA) D6 LBA This bit is set to 1. LBA is a flag to select either Cylinder/Head/Sector (CHS) or Logical Block Address Mode D5 1 D4 DRV D3 HS3 D2 HS2 D1 HS1 D0 HS0 (LBA). When LBA=0, Cylinder/Head/Sector mode is selected. When LBA = 1, Logical Block Address is selected. In Logical Block Mode, the Logical Block Address is interpreted as follows: LBA7-LBA0: LBA15-LBA8: LBA23-LBA16: LBA27-LBA24: Bit 5 Bit 4 (DRV) 1 This bit is set to 1. DRV is the drive number. When DRV 0, drive (card) 0 is selected. When DRV = 1,drive Sector Number Register D7-D0. Cylinder Low Register D7-D0. Cylinder High Register D7-D0. Drive/Head Register HS3-HS0. (card) 1 is selected. The PC Card is set to be Card 0 or 1 using the copy field (Drive #) of the PCMCIA Socket & Copy configuration register. Bit 3 (HS3) When operating in the Cylinder, Head, Sector mode, this is bit3 of the head number. It is Bit 27 in the Logical Block Address mode. Bit 2 (HS2) When operating in the Cylinder, Head, Sector mode, this is bit2 of the head number. It is Bit 26 in the Logical Block Address mode. Bit 1 (HS1) When operating in the Cylinder, Head, Sector mode, this is bit1 of the head number. It is Bit 25 in the Logical Block Address mode. Bit 0 (HS0) When operating in the Cylinder, Head, Sector mode, this is bit0 of the head number. It is Bit 24 in the Logical Block Address mode 46 S3C49F9X SOLID DISK CONTROLLER CARD CONFIGURATION 4.10.9 Status & Alternate Status Register (Address -1F7[177]&3F6[376]; Offset 7, Eh): These registers return the PC Card status when read by the host. Reading the Status register does clear a pending interrupt while reading the Auxiliary Status register does not. The meaning of the status bits is described as follows: D7 BUSY Bit 7 (BUSY) D6 RDY D5 DWF D4 DSC D3 DRQ D2 CORR D1 0 D0 ERR The busy bit is set when the PC Card has access to the command buffer and registers and the host is locked out from accessing the command register and buffer. No other bits in this register are valid when this bit is set to a 1. Bit 6 (RDY) RDY indicates whether the device is capable of performing PC Card operations. This bit is cleared at power up and remains cleared until the PC Card is ready to accept a command. Bit 5 (DWF) Bit 4 (DSC) Bit 3 (DRQ) This bit, if set, indicates a write fault has occurred. This bit is set when the PC Card is ready. This bit is cleared at power up. The Data Request is set when the PC Card required and that information be transferred either to or from the host through the Data register. Bit 2 (CORR) This bit is set when a Correctable data error has been encountered and the data has been corrected. This condition does not terminate a multi-sector read operation. Bit 1 This bit is always set to 0. Bit 0 (ERR) This bit is set when the previous command has ended in some type of error. The bits in the Error register contain additional information describing the error. 47 S3C49F9X SOLID DISK CONTROLLER CARD CONFIGURATION 4.10.10 Device Control Register (Address -3F6[376]; Offset Eh): This register is used to control the PC Card interrupt request and to issue an ATA soft reset to the card. This register can be written even if the device is BUSY. The bits are defined as follows: D7 x D6 x D5 x D4 x D3 1 D2 SW Rst D1 -IEn D0 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 This bit is an X (don't care). This bit is an X (don't care). This bit is an X (don't care). This bit is an X (don't care). This bit is ignored by the PC Card. Bit 2(SW Rst) This bit set to 1 in order to force the PC Card to perform an AT Disk controller Soft Reset operation. This does not change the PCMCIA Card Configuration Registers (4.3.2-to 4.3.5) as hardware Reset does. The Card remains in Reset until this bit is reset to "0". Bit 1 The Interrupt Enable bit enables interrupts when the bit is 0 (-IEn=0), interrupts from the PC Card are disable. This bit also controls the Int bit in the Configuration and Status Register. This bit is set to 1 at power on and Reset. Bit 0 This bit ignored by the PC Card. 48 S3C49F9X SOLID DISK CONTROLLER CARD CONFIGURATION 4.10.11 Card (Drive) Address Register (Address -3F7[377]; Offset Fh): This register is provided for compatibility with the AT disk drive interface. It is recommended that this register nit be mapped into the host's I/O space because of potential conflicts on Bit 7. The bits are defined as follow: D7 x Bit 7 D6 -WTG D5 -HS3 D4 -HS2 D3 -HS1 D2 -HS0 D1 -nDS1 D0 -nDS0 This bit is unknown. Implementation Note: Conflicts may occur on the host data bus when this bit is provided by a Floppy Disk Controller operating at the same addresses as the PC Card. Following are some possible solutions to this problem for the PCMCIA implementation: 1.Locate the PC Card at a non -conflicting address, i.e. Secondary address (377h) or in an independently decoded Address Space when a Floppy Disk Controller is located at the Primary addresses. 2.Do not install a Floppy and a PC Card in the system at the same time. 3.Implement a socket adapter which can be programmed to (conditionally) tri-state D7 of I/O address 3F7h/377h when a PC Card is installed and conversely to tri-state D6-D0 of I/O address 3F7h/377h when a floppy controller is installed. 4.Do not use the PC Card's Drive Address register. This may be accomplished by either If possible, program the host adapter to enable only I/O address 1F0h-1F7h, 3F6h (or 170-177h, 176h) to the PC Card or If provided use an additional Primary/Secondary configuration in the PC Card which does not respond to accesses to I/O location 3F7h and 377h with either of these implementation, the host software must not attempt to use information in the Drive Address Register. Bit 6 (-WTG) This bit is 0 when a write operation is in progress, otherwise, it is 1. Bit 5 (-HS3) This bit is the negation of bit 3 in the Drive/Head register. Bit 4 (-HS2) This bit is the negation of bit 2 in the Drive/Head register. Bit 3 (-HS1) This bit is the negation of bit 1 in the Drive/Head register. Bit 2 (-HS0) This bit is the negation of bit 0 in the Drive/Head register. Bit 1 (-nDS1) This bit is 0 when drive 1 is active and selected Bit 0 (-nDS0) This bit is 0 when the drive 0 is active and selected. 49 S3C49F9X SOLID DISK CONTROLLER CARD CONFIGURATION 4.11 ATA Command Description This section defines the software requirements and the format of the commands the host sends to the PC Cards. Command are issued to the PC Card by loading the required registers in the command block with the supplied parameters, and then writing the command code to the Command Register. The manner in which a command is accepted varies. There are three classes (see Table 6-1) of command acceptance, all dependent on the host not issuing commands unless the PC Card is not busy (BSY = 0). 4.11.1 Vendor Unique Command Bit-> Command (7) C/D/H (6) Cylinder High (5) Cylinder Low (4) Sec Number (3) Sec Count(2) Feature (1) x 7 6 5 4 EFH 3 2 x 1 0 Drive x x x Config Feature A Vendor unique command is setting F0h as Feature REGISTER of a SET FEATURE COMMAND, and is executed. Moreover, each Vendor unique command is processed with the setting value of Config. Set Features Command(EF h) ConfigFeature Value = F0h Config Value C0 C1 C2 C3 C4 C5 C6 C7 C8 Note1 Command Name Physical Read Physical Write Physical Block Erase Set SG Control Table Flash initialize Change Information CIS/DID Get Flash Information Get Firmware Revision Get Flash ID Information Description Read from physical page on flash memory. Write data to physical page on flash memory. Erase physical block on flash memory. Set SG Control Table for initializing Flash Memory Executing Flash Memory initializing. Changing Data of CIS/DID. Getting flash Memory information. (Structure of Block number and Page number.) Getting Firmware Revision. Getting flash information of Maker ID and Device ID. 50 S3C49F9X SOLID DISK CONTROLLER CARD CONFIGURATION 4.11.2 Physical Read Sector Bit-> Command (7) C/D/H (6) Cylinder High (5) Cylinder Low (4) Sec Number (3) Sec Count(2) Feature (1) x Drive Page No High Page No Low Chip No (0-31) C0h F0h 7 6 5 4 EFH x 3 2 1 0 Features code F0h enables the host to configure the card to test card function. The host sets a value C0h in the Sector Count register that is permission physical sector access. The Physical Read Sector command performs similarly to the Read Sector(s) command except that it returns 528 bytes from physical sector (flash page). During a Physical Read Sector command, the PC Card does not check the ECC bytes to determine if there has been a data error. Only single sector Read long operations are supported. The transfer consists of 512 bytes of data transferred in word mode followed by 16 bytes of spare data transferred in byte mode. This command has the same protocol as the Read Sector(s) command. Use of this command is Developer's test. Input parameter l Cylinder High Low = The page address within a memory chip. (0Sector Number = Memory chip number. (0-31) l The output parameter at the time of a normal end Status Register = 50h The output parameter at the time of an unusual end. l An address is too large. Status Register = 51h Error Register = 10h(ID Not Found) ) 51 S3C49F9X SOLID DISK CONTROLLER CARD CONFIGURATION 4.11.3 Physical Write Sector Bit-> Command (7) C/D/H (6) Cylinder High (5) Cylinder Low (4) Sec Number (3) Sec Count(2) Feature (1) x Drive Page No High Page No Low Chip No (0-31) Ch F0h 7 6 5 4 EFH x 3 2 1 0 The Physical Write Sector command performs similarly to the Write Sector(s) command except that it writes 528 bytes of data instead of 512 bytes. During a Physical Write Sector command, the PC Card does not check the ECC bytes to determine if there has been a data error. Only single page Write operations are supported. The transfer consists of 512 bytes of data transferred in word mode followed by 16 bytes of spare data transferred in byte mode. This command has the same protocol as the write Sector(s) command. Use of this command is Developer's test. Input parameter l Cylinder High Low = The page address within a memory chip. (0Sector Number = Memory chip number. (0-31) The output parameter at the time of a normal end l Status Register = 50h The output parameter at the time of an unusual end. l An address is too large. Status Register = 51h Error Register = 10h(ID Not Found) Write fault. l Status Register = 71h(Write fault) Error Register = 80h(Bad Block Detected) ) 52 S3C49F9X SOLID DISK CONTROLLER CARD CONFIGURATION 4.11.4 Physical Erase Block Bit-> Command (7) C/D/H (6) Cylinder High (5) Cylinder Low (4) Sec Number (3) Sec Count(2) Feature (1) x Drive Block No High Block No Low Chip No (0-31,FFh) Ch F0h 7 6 5 4 EFH x 3 2 1 0 CF which a command was taken in does elimination toward physical Block of the specified chip Number. It is the erase of only one block. A Sec Number of FFh requests all block Erase. Block No is Block Address in a tip simple substance. 4.11.5 Set SG(Sector Group)Control Table Bit-> Command (7) C/D/H (6) Cylinder High (5) Cylinder Low (4) Sec Number (3) Sec Count(2) Feature (1) x Drive The number of link blocks The number of spared part blocks The number of updated part blocks C3h F0h 7 6 5 4 EFH x 3 2 1 0 A garbage collection is performed. This Command must be executed before Initialize Flash Memory Command. 53 S3C49F9X SOLID DISK CONTROLLER CARD CONFIGURATION 4.11.6 Initialize Flash Memory Bit-> Command (7) C/D/H (6) Cylinder High (5) Cylinder Low (4) Sec Number (3) Sec Count(2) Feature (1) x Drive x Number of mounted Flash Memory Erase Flash Switch C4h F0h 7 6 5 4 EFH x 3 2 1 0 This command checks all flash memory, and after then, write information of control. The blank check of all the mounting flash memories is done, and Write/Read/Compare/Erase is done, and writing a control table are made (initialization to do after mounting). Sec Number :When This Value is FFh, Erase block of all the mounting flash memories. Note. Before this Command execution, all blocks must be erased. After this Command execution, it must execute the Write CIS/DID Command (Change Card Information). Error return value (Sec Number) Error Value 00h 01h 02h 03h 04h 05h Description Normalcy End: it is Sec Number =00h. All flash chip is not recognized by ID read command. Block 0 or Block 1 erase check error. Block 0 or Block 1 write/read check error. CIS/DID Write page error Link info writes error or SG ctbl (The table of control information) build up error. 54 S3C49F9X SOLID DISK CONTROLLER CARD CONFIGURATION 4.11.7 Change Card Information Bit-> Command (7) C/D/H (6) Cylinder High (5) Cylinder Low (4) Sec Number (3) Sec Count(2) Feature (1) x Drive Interleave Mode FAT Analysis Mode x C5h F0h 7 6 5 4 EFH x 3 2 1 0 This command change card information. As for doing action, writing of CIS/DID and Flash Information to page of the fixation, others is the same protocol as Write Sector Command the elimination of the fixed block. But Flash information currently written in is inherited, without updating. Format of writes data (format) Byte 0-255 256-511 Description CIS(Vendor Unique) Drive Identify Information(Vendor Unique) Special specification(Note) Specification Interleave FAT Analysis Set Register Cylinder High Cylinder Low Function 2F:Enable, 1Fh:Disable FA:Enable, F0h:Disable Data of Special specification are written on Flash memory (1Byte). That location is Page No.1 of Block No.0. Data after 2 byte is invalid. Default is Disable (FFh). Note: This specification is not supported now. 55 S3C49F9X SOLID DISK CONTROLLER CARD CONFIGURATION 4.11.8 Get Flash chip Information Bit-> Command (7) C/D/H (6) Cylinder High (5) Cylinder Low (4) Sec Number (3) Sec Count(2) Feature (1) x Drive x x x C6h F0h 7 6 5 4 EFH x 3 2 1 0 This command checks connecting flash chip information. The PC Card sets Sector Number Register to Page number per block, Cylinder Low Register to Block number LSB, Cylinder High Register to Block number MSB. 4.11.9 Get Firmware Information Bit-> Command (7) C/D/H (6) Cylinder High (5) Cylinder Low (4) Sec Number (3) Sec Count(2) Feature (1) x Drive x x x C7h F0h 7 6 5 4 EFH x 3 2 1 0 This command checks the Firmware Revision. The PC Card sets Sector Number Register to firmware version. Firmware Revision A.B Return parameter: Sector Number = Firmware Revision Byte (A). Cylinder Low = Firmware Revision Byte (B). 56 S3C49F9X SOLID DISK CONTROLLER CARD CONFIGURATION 4.11.10 Get Flash ID Information Bit-> Command (7) C/D/H (6) Cylinder High (5) Cylinder Low (4) Sec Number (3) Sec Count(2) Feature (1) x Drive x x x C8h F0h 7 6 5 4 EFH x 3 2 1 0 This command checks connecting flash chip information. The PC Card sets Sector Number Register to mounting chip number, Cylinder Low Register to maker ID, Cylinder High Register to device ID. 57 S3C49F9X SOLID DISK CONTROLLER CARD CONFIGURATION 4.12 Card Information Structure(Default) Attribut e Offset 000h 002h 004h 01 04 DF Device Type Code Dh=I/O 006h 008h 00Ah 00Ch 4A 01 FF 1C X Device Size List End Marker CISTPL_DEVICE_OC 9h W 1 Speed 7h 2h CISTPL_DEVICE Device Info Tuple Link is 4bytes I/O device, No Write Protects, Device Speed = 400ns 2Kbyte of address Space End of Devices Other Condition Device Info Tuple 00Eh 010h 012h 04 02 D9 0 Reserved, 0 W 1 VccU Speed 1h M Link is 4bytes 3.3V Vcc Operation I/O device, No Write Protects, Device Speed=250ns 014h 016h 018h 01 FF 18 Device Size List End Marker CISTPL_JEDEC_C 2Kbyte of address Space End of Devices JEDEC Mem 01Ah 01Ch 02 DF PCMCIA Manufacture's ID Link is 2bytes First Byte of JEDEC ID Link to next tuple JEDEC Device 1 01Eh 01 PCMCIA Code for PC Card-ATA No Second Byte of JEDEC JEDEC ID Vpp Required 020h 022h 024h 026h 028h 02Ah 02Ch 20 04 CE 00 00 00 15 CISTPL_VERS_1 Level 1 Version/Product Information 02Eh 20 Link is 20bytes Link to next tuple Manufacture Information PC Card Manufacture's ID Code CISTPL_MANFID ID Manufacture ID String Link is 4bytes Tuple Code Link to next tuple TPLMID_MANF TPLMID_MANF TPLMID_CARD TPLMID_CARD Tuple Code ID of ID Common Device Size End Marker Tuple Code Link to next tuple OC Info Device ID WPS, Speed Device Size End Marker Tuple Code Tuple Code Link to next tuple Device ID WPS, Speed Data 7 6 5 4 3 2 1 0 Description of Contents CIS Function Device Type Code Dh=I/O 58 S3C49F9X SOLID DISK CONTROLLER CARD CONFIGURATION 030h 032h 034h 036h 038h 03Ah 03Ch 03Eh 040h 042h 044h 046h 048h 04Ah 04Ch 04Eh 050h 052h 054h 056h 058h 05Ah 05Ch 05Eh 060h 062h 064h 066h 068h 06Ah 06Ch 06Eh 070h 072h 04 01 53 41 4D 53 55 4E 47 20 20 20 20 20 20 00 53 43 46 44 2D 56 45 52 31 2E 30 20 20 00 00 FF 21 02 Major Version Number Minor Version Number Manufacture Information PCMCIA 2.1 JEIDA 4.2 Name of Manufacture TPLLV1_MAJOR TPLLV1_MINOR String 1 "SAMSUNG" End of Manufacture Information Product Information Null Terminator Name of Product End String 1 String 2 "SCFD-VER1.0" End of Product Information End of CIS Revision Number List End Marker CISTPL_FUNCID Null Terminator Null Terminator End String 2 End Marker Function ID Tuple Link is 2bytes Tuple Code Link to next tuple 59 S3C49F9X SOLID DISK CONTROLLER CARD CONFIGURATION 074h 04 IC Card Function Code Fixed Disk Function TPLFID_FUNCTIO N 076h 01 RFU, 0 R P System Initialization Bit Mask, Power-On-Self Test TPLFID_SYSINIT 078h 22 CISTPL_FUNCE Function Tuple Extention Tuple Code 07Ah 07Ch 07Eh 080h 02 01 01 22 Disk Function Extension Tuple Type Interface Type Code CISTPL_FUNCE Link is 2bytes Disk Device Interface PC Card-ATA Interface Function Tuple Extention Link to next tuple TPLFE_TYPE TPLFE_DATA Tuple Code 082h 084h 086h 03 02 0C Disk Function Extension Tuple Type RFU U S V Link is 3bytes Disk Device Interface Silicon/Rotating, ID/SN is unique, Link to next tuple TPLFE_TYPE TPLFE_DATA 088h 0F R I E N P3 P2 P1 P0 Auto, Idle, Standby, Sleep Mode supported TPLFE_DATA 08Ah 08Ch 08Eh 090h 1A 05 01 03 CISTPL_CONFIG Configuration Tuple Link is 5bytes Tuple Code Link to next tuple TPCC_SZ Last entry of RFSZ TPCC_LAST RMSZ RASZ Size of Fields Byte Entry Index 03h Configuration table 092h 00 TPCC_RADR Configuration Registers are located at 200h 094h 096h 02 0F TPCC_RADR RFU S P C I 4 Configuration TPCC_RMSK Location of Config Registers Registers are present 098h 1B CISTPL_CFTABLE_ENTRY Configuration Tuple 09Ah 09Ch 08 C0 I D Configuration Entry Number Link is 8bytes Memory Mapped I/O, D: Configuration, I: Interface Byte Follows Default Link to next tuple TPCE_INDX Entry Tuple Code 60 S3C49F9X SOLID DISK CONTROLLER CARD CONFIGURATION 09Eh C0 M W R W P B V Interface Type Memory Only Interface, Bvd & WP not used, RDY/BSY & Wait used for Memory Cycle TPCE_IF 0A0h A1 M MS IR Q IO T Power Vcc power-description structure only, MS: Single 2-byte length specified M: Misc field structure is present TPCE_FS 0A2h 01 R DI PI AI SI H V L V N V Nominal Operating Supply Voltage, No Extension Power for Vcc Parameters 0A4h 0A6h 55 08 X Ah 5h Vcc Noninal is 5V Length of Mem Space is 2KB Vcc Nominal Value TPCE_MS Length LSB TPCE_MS Length MSB Length in 256 bytes pages(LSB) 0A8h 00 Length in 256 bytes pages(MSB) Start at 0 on Card 0AAh 0ACh 20 1B X R P R A Twin Power Down Configuration Entry Tuple TPCE_MI Tuple Code CISTPL_CFTABLE_ENTRY 0AEh 0B0h 06 00 I D Configuration Number Entry Link is 6bytes Link to next tuple TPCE_INDX 0B2h 01 M MS IR Q IO T Power Vcc power-description structure only TPCE_FS 0B4h 21 R DI PI AI SI H V L V N V Maximum Current required averaged over 10ms, Nominal Operating Supply Voltage, With Extension TPCE_PD 0B6h 0B8h 0BAh B5 1E 4D X X X 6h 1Eh(30d) 9h 5h 1V x 3 Vcc Nominal is 3.3V Vcc Nominal Value 5h Peak I is 45mA Peak I Value 61 S3C49F9X SOLID DISK CONTROLLER CARD CONFIGURATION 0BCh 1B CISTPL_CFTABLE_ENTRY Configuration Entry Tuple Tuple Code 0BEh 0C0h 0A C1 I D Configuration Number Link is 10bytes Entry I/O Mapped Contiguous 16 Registers Configuration, D: Configuration, I: Interface Byte Follows Default Link to next tuple TPCE_INDX 0C2h 41 W R P B Interface Type I/O Interface, Bvd & WP not used, RDY/BSY active, Wait not used for memory access TPCE_IF 0C4h 99 M MS IR Q IO T Power Misc & IRQ field are present, Vcc power-description structure only TPCE_FS 0C6h 01 R DI PI AI SI H V L V 5h N V Nominal Operating supply Voltage Vcc Nominal is 5V Support 16/8 bit I/O access, I/O Address Lines are 16 TPCE_PD 0C8h 0CAh 55 64 X R Bus 16/8 Ah Vcc Nominal Value TPCE_IO I/O AddrLines 0CCh F0 S P L M V B I N IRQ Sharing S: Share Logic active, P: Pulse IRQ supported, L: Level IRQ supported, M: Bit Mask of IRQ TPCE_IR 0CEh FF IRQ Levels to be routed TPCE_IR 0-7 recommended Mask Extension 0D0h FF IRQ Levels to be routed TPCE_IR 8-15 recommended Mask Extension TPCE_MI 0D2h 20 X R P R O A T Power Down supported 62 S3C49F9X SOLID DISK CONTROLLER CARD CONFIGURATION 0D4h 1B CISTPL_CFTABLE_ENTRY Configuration Entry Tuple Tuple Code 0D6h 0D8h 06 01 I D Configuration Number Entry Link is 6bytes Link to next tuple TPCE_INDX 0DAh 01 M MS IR Q IO T Power Vcc power-description TPCE_FS structure only SI H V L V N V Nominal Operating supply Voltage, Maximum Current required averaged over 10ms TPCE_PD 0DCh 21 R DI PI AI 0DEh 0E0h 0E2h 0E4h B5 1E 4D 1B X X X 6h 1Eh(30d) 9h 5h 1V x 3 Vcc Nominal is 3.3V Vcc Nominal Value 5h Peak I is 45mA Configuration Entry Tuple Peak I Value Tuple Code CISTPL_CFTABLE_ENTRY 0E6h 0E8h 0F C2 I D Configuration Number Entry Link is 15bytes Link to next tuple TPCE_INDX 0EAh 41 W R P B Interface Type I/O Interface, Bvd & WP not used, RDY/BSY active, Wait not used for memory access TPCE_IF 0ECh 99 M MS IR Q IO T Power Misc & IRQ field are present, Vcc power-description structure only TPCE_FS 0EEh 01 R DI PI AI SI H V L V 5h N V Nominal Operating supply Voltage Vcc Nominal is 5V TPCE_PD 0F0h 55 X Ah Vcc Nominal Value 63 S3C49F9X SOLID DISK CONTROLLER CARD CONFIGURATION 0F2h EA R Bus 16/8 I/O AddrLines I/O range description, Support 16/8 bit I/O access, A 1 Kbyte I/O address space TPCE_IO 0F4h 61 Size of length Size of address Number of I/O Address Ranges Length is 1 byte long, Address is 2 byte long, 1 I/O Address Range Description field I/O Range Description Byte 0F6h 0F8h 0FAh 0FCh F0 01 07 F6 Start of I/O Address Block First(LSB) Start of I/O Address Block First(MSB) First I/O Range Length Start of I/O Address Block Second(LSB) 0FEh 03 Start of I/O Address Block Second(MSB) 100h 102h 01 EE Second I/O Range Length S P L M V B I N IRQ Sharing S: Share Logic active, P: Pulse IRQ supported, L: Level IRQ supported, V: Vendor-Specific supported, B: Bus-Error supported, I: I/O-check supported 104h 20 X R P R O 106h 1B CISTPL_CFTABLE_ENTRY Configuration Entry Tuple 108h 10Ah 06 02 I D Configuration Number 10Ch 01 M MS IR Q 10Eh 21 R DI PI AI SI H V L V N V IO T Power Vcc power-description structure only Nominal Operating supply Voltage, TPCE_PD TPCE_FS Entry Link is 6bytes Link to next tuple TPCE_INDX Tuple Code A T Power Down supported TPCE_MI TPCE_IR 64 S3C49F9X SOLID DISK CONTROLLER CARD CONFIGURATION Maximum Current required averaged over 10ms 110h 112h 114h 116h B5 1E 4D 1B X X X 9h 6h 1Eh(30d) 5h 5h 1V x 3 Vcc Nominal is 3.3V Peak I is 45mA Configuration Tuple 118h 11Ah 0F C3 I D Configuration Number 11Ch 41 W R P B Interface Type I/O Interface, Bvd & WP not used, RDY/BSY active, Wait not used for memory access 11Eh 99 M MS IR Q IO T Power Misc & IRQ field are present, Vcc power-description structure only 120h 01 R DI PI AI SI H V 122h 124h 55 EA X R Bus 16/8 Ah L V 5h I/O AddrLines N V Nominal Operating supply Voltage Vcc Nominal is 5V I/O range description, Support 16/8 bit I/O access, A 1 Kbyte I/O address space 126h 61 Size of length Size of address Number of I/O Address Ranges Length is 1 byte long, Address is 2 byte long, 1 I/O Address Range Description field 128h 12Ah 12Ch 70 01 07 Start of I/O Address Block First(LSB) Start of I/O Address Block First(MSB) First I/O Range Length I/O Range Vcc Nominal Value TPCE_IO TPCE_PD TPCE_FS TPCE_IF Entry Link is 15bytes Link to next tuple TPCE_INDX Entry Peak I Value Tuple Code Vcc Nominal Value CISTPL_CFTABLE_ENTRY Description Byte 65 S3C49F9X SOLID DISK CONTROLLER CARD CONFIGURATION 12Eh 76 Start of I/O Address Block Second(LSB) 130h 03 Start of I/O Address Block Second(MSB) 132h 134h 01 EE Second I/O Range Length S P L M V B I N IRQ Sharing S: Share Logic active, P: Pulse IRQ supported, L: Level IRQ supported, V: Vendor-Specific supported, B: Bus-Error supported, I: I/O-check supported 136h 20 X R P R O 138h 1B CISTPL_CFTABLE_ENTRY Configuration Entry Tuple 13Ah 13Ch 06 03 I D Configuration Number 13Eh 01 M MS IR Q 140h 21 R DI PI AI SI H V L V N V IO T Power Vcc power-description structure only Nominal Operating supply Voltage, Maximum Current required averaged over 10ms 142h 144h 146h 148h B5 1E 4D 14 X X X 9h 6h 1Eh(30d) 5h 5h 1V x 3 Vcc Nominal is 3.3V Peak I is 45mA No Link to Common Memory 14Ah 14Ch 00 FF No Bytes Following End of CIS Tuple Chain Link Length is 0 byte End of CIS Link to next tuple Tuple Code Peak I Value Tuple Code Vcc Nominal Value TPCE_PD TPCE_FS Entry Link is 6bytes Link to next tuple TPCE_INDX Tuple Code A T Power Down supported TPCE_MI TPCE_IR CISTPL_NO_LINK 66 S3C49F9X SOLID DISK CONTROLLER CARD CONFIGURATION 4.13 Example test of production (1) Modules check. (2) Set feature Command code C4 Check Flash Memory. Initialization Table. Managed table creation. Write CIS/DIDFLASH. (4) Card check. (function) Physical Disk Format Logical Disk Format Read/Write check Note : (Initialize Flash Memory) (Initialize Flash Memory) (Initialize Flash Memory) (Change Information) ATAINITDOS FORMATDOS SCANDISKDOS Set Parameter FAT16,FAT32,NTFS etc. (3) Set feature Command code C5 ATAINIT is a Card Wizard utility that create a DOS partition on the FlashDisk card. ATAINIT program(the System Soft Corp FDISK utility). 4.14 Load of CIS Card Information Structure DID Drive Identify Data - The foundations of CIS are defined as the firmware of ARM7TDMI. (Definition of only 5V power supply.) - When effective data as CIS does not have data in head block of a flash or flash is not mounted, data defined as the firmware is loaded as CIS. - When there is CIS developed to the flash (After CIS and DID are written), its data become effective, CIS is read from a flash. - DID is not defined in first stage. - The write of CIS/DID and the code of rewriting are put on the first page of first block of a flash, and access to other blocks is not performed (management TBL etc. is not changed). - CIS/DID needs to be rewritten with the specification of a card. - Concept figure (CIS/DID Load action). 4.15 Power On Error Specification when an internal initialization error happens is explained at the time of power-supply starting. When failing in initialization, the following bit is set as ERROR Register and status is set to RDY. ERROR Register bit Bit1 Bit3 Bit5 Description flash ROM read ID error or reset error CIS read error (error occurred even when CIS in ROM is used) link block read error 67 S3C49F9X SOLID DISK CONTROLLER APPLICATION NOTE 5 ELECTRICAL DATA OVERVIEW In this section, S3C49F9X electrical characteristics are presented in tables and graphs. The information is arranged in the following order: -- Absolute maximum ratings -- Recommended operating conditions -- Thermal characteristics 59 S3C49F9X SOLID DISK CONTROLLER APPLICATION NOTE Table 5-1. Absolute Maximum Ratings Symbol VDD VIN I IN T STG Parameter Supply voltage Input voltage DC input current Storage temperature - 40 Ratings - 0.3 - 0.3 to to + 7.0 Unit V V mA + 125 C VDD + 0.3 - 10 to Table 5-2. Recommended Operating Conditions Symbol VDD Ta Parameter DC supply voltage 5V 3.3 V Storage temperature 4.75 3.0 - 40 Ratings to to to + 5.25 3.6 + 85 Unit V V C Table 5-3. Thermal Characteristics Symbol ja Parameter Thermal impedance - junction to ambient plastic 144-pin LQFP Value 57 Unit C /W 60 S3C49F9X SOLID DISK CONTROLLER APPLICATION NOTE Table 5-4. D.C. Electrical Characteristics (TA VIH VIL VT VT+ VTIIH = 0 to 70 C, VDD = 3.3 V 0.3 V) Conditions CMOS CMOS CMOS CMOS CMOS Input buffer Input buffer with pull-up IIL Low level input current Input buffer Input buffer with pull-up VOH High level output voltage Type 4 Type 4 Type 4 VOL Low level output voltage Type 4 Type 4 Type 4 IOZ IDD Iidle Ids Tri-state output leakage current Maximum operating current Idle current Stop current (1) (2) (3) (1) (2) (3) Symbol Parameter High level input voltage Low level input voltage Switching threshold Switching trigger, positivegoing threshold Switching trigger, negativegoing threshold High level input current Min 2.0 Typ Max Unit V 1.0 1.4 2.0 1.0 VIN = V DD -10 10 VIN = V SS -10 -160 IOH = -4 mA IOH = -8 mA IOH = -16 mA IOH = 4 mA IOH = 8 mA IOH = 16 mA VOUT = V SS or VDD VDD = 5.0 V, fMCLK = 20 MHz -10 30 10 40 20 30 0.4 2.4 -30 30 10 60 10 -10 V V V V uA uA V V uA mA mA uA NOTES: 1. 4 mA drive output PAD. 2. 8 mA drive output PAD. 3. 16 mA drive output PAD. 61 S3C49F9X SOLID DISK CONTROLLER APPLICATION NOTE Table 5-4. D.C. Electrical Characteristics (TA VIH VIL VT VT+ = 0 to 70 C, VDD = 5V 5 %) Conditions CMOS TTL Low level input voltage CMOS TTL Switching threshold CMOS TTL Switching trigger, positivegoing threshold Switching trigger, negativegoing threshold High level input current CMOS TTL VTCMOS TTL IIH Input buffer Input buffer with pull-up IIL Low level input current Input buffer Input buffer with pull-up VOH High level output voltage Type 4 Type 4 Type 4 VOL Low level output voltage Type 4 Type 4 Type 4 IOZ IDD Iidle Ids Tri-state output leakage current Maximum operating current Idle current Stop current (1) (2) (3) (1) (2) (3) Symbol Parameter High level input voltage Min 3.5 2.0 Typ Max Unit V 1.5 0.8 2.5 1.4 4.0 2.0 1.0 0.8 VIN = V DD -10 10 VIN = V SS -10 -100 IOH = -4 mA IOH = -8 mA IOH = -16 mA IOH = 4 mA IOH = 8 mA IOH = 16 mA VOUT = V SS or VDD VDD = 5.0 V, fMCLK = 20 MHz -10 60 10 70 35 60 0.4 2.4 -50 50 10 100 10 -10 V V V V uA uA V V uA mA mA uA NOTES: 1. 4 mA drive output PAD. 2. 8 mA drive output PAD. 3. 16 mA drive output PAD. 62 S3C49F9X SOLID DISK CONTROLLER APPLICATION NOTE 6 MECHANICAL DATA OVERVIEW The S3C49F9X disk controller is available in a 100-pin TQFP package (Samsung part number 100-TQFP-1414)/ 16.00 BSC 14.00 BSC 0-7 0.127 + 0.073 - 0.037 16.00 BSC 14.00 BSC 100-TQFP-1414 0.08 MAX #100 #1 0.50 + 0.07 0.20 - 0.03 0.08 MAX 0.05-0.15 (1.00) 1.00 0.05 1.20 MAX NOTE: Dimensions are in millimeters. Figure 6-1. 100-TQFP-1414 Package Dimension 0.45-0.75 63 S3C49F9X SOLID DISK CONTROLLER APPLICATION NOTE 7 APPLICATION NOTE FLASH MEMORY CONNECTION FRDY0 FCLE0 FALE0 FWE0 FRE0 Flash 0 Flash 1 Flash 2 Flash 9 FCE0 FCE1 FCE2 ... FCE9 FDB[7:0] Figure 7-1. Case of Using the S3C49F9X 64 |
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